期刊論文

H.Y. Kao, S.H. Huang and W.K. Cheng, "Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation", Electronics, vol. 11, no. 13, Article 2107, 2022. (SCI)
Y.K. Weng, S.H. Huang and H.Y. Kao, “Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations”, Sensors, vol. 21, no. 22, Article 7468, 2021. (SCI)
H.Y. Kao, X.J. Chen and S.H. Huang, “Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing”, Sensors, vol. 21, no. 15, Article 5081, 2021. (SCI)
C.W. Tung, S.H. Huang, "A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process”, IEEE Access, Vol. 8, pp. 87367-87377, 2020. (SCI)
C.H. Chou, Y.T. Lai, Y.C. Chang, C.Y. Wang, L.C. Cheng, S.H. Huang, S.C. Chang, "Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No. 1, pp. 146-155, 2017. (SCI) (NSC 102-2221-E-033-064-MY3)
S.H. Huang and C.H. Cheng, "Power-Mode-Aware Buffer Synthesis for Low-Power Clock Skew Minimization”, IEICE Electronics Express (ELEX), Vol. 13, No. 14, pp. 1-12, 2016. (SCI) (NSC 102-2221-E-033-064-MY3)
S.H. Huang, C.H. Chiu, C.H. Cheng, and T.J. Wang, "Simultaneous Test Scheduling and TAM Bus Wire Assignment for Temperature-Dependent Core-Based SoC Testing”, International Journal of Electrical Engineering (IJEE), Vol. 23, No. 2, pp. 53-62, 2016. (invited for publication in the VLSI Design/CAD Symposium special issue) (EI) (MOST 104-2220-E-033-001)
C.H. Chou, H.H. Yeh, S.H. Huang, Y.T. Nieh, S.C. Chang, and Y.T. Chang, "Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 3, pp. 1189-1192, 2016. (SCI) (NSC102-2221-E-033-064-MY3)
S.H. Huang, H.H. Yeh, and Y.T. Nieh, "Clock Period Minimization with Minimum Leakage Power”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 21, No. 1, Article 9. 2015. (SCI) (NSC99-2221-E-033-061-MY3)
T.T. Lin, W.P. Tu, and S.H. Huang, "Self-Adjusting Mechanism for Reducing the Impact of PVT Variations on Clock Skew”, International Journal of Electrical Engineering (IJEE), Vol. 21, No. 6, pp. 225-234, 2015. (invited for publication in the VLSI Design/CAD Symposium special issue) (EI) (MOST 102-2221-E-033-064-MY3)
S.H. Huang and H.H. Yeh, "Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits" ,IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol.-97-A, No. 8, pp. 1699-1708, 2014.(SCI)(NSC100-2221-E-033-024-MY3)
S.H. Huang, W.P. Tu, C.M. Chang, and S.B. Pan, "Low-Power Anti-Aging Zero Skew Clock Gating", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vo. 18, No. 2, Article 27, 2013. (NSC97-2221-E-033-053-MY3)
S.H. Huang, W.P. Tu, and B.H. Li, "High-Level Synthesis for Minimum-Area Low-Power Clock Gating", Journal of Information Science and Engineering (JISE), Vol. 28, No. 5, pp. 971-988, 2012. (SCI)
S.H. Huang, G.Y. Jhuo, and W.L. Huang, "Minimum Inserted Buffers for Clock Period Minimization", Journal of Information Science and Engineering, Vol. 27, No.5, pp. 1513-1526, 2011.(SCI) (NSC99-2221-E-033-061-MY3)
C.H. Lee, S.H. Huang, and C.H. Cheng, "Accurate TSV Number Minimization in High-Level Synthesis", Journal of Information Science and Engineering, Vol.27, No.5, pp.1527-1543, 2011.(SCI) (NSC97-2221-E-033-053-MY3)
S.H. Huang and C.H. Cheng, "Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization", Journal of Information Science and Engineering, vol. 26, no. 6, pp. 2249-2266, 2010,11. (SCI) (NSC96-2628-E-033-004-MY3)
S.H. Huang,C.H. Cheng, and S.B. Pan, "Synthesis of Anti-Aging Gated Clock Designs",Journal of Information Science and Engineering, vol. 25, No. 6, pp. 1651—1670, 2009. (SCI) (NSC97-2221-E-033-053-MY3)
S.H. Huang,C.H. Cheng,and D.C. Tzeng, "Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization", Journal of Information Science and Engineering, vol 25, vo. 6, pp. 1707-1722,2009. (SCI) (NSC96-2628-E-033-004-MY3)
S.H. Huang and C.H. Cheng, "Minimum-Period Register Binding", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.28, no. 8, pp. 1265-1269, 2009,08. (SCI) (NSC95-2221-E-033-075-MY2)
S.H. Huang, J.F. Yeh, and C.H. Cheng, "An ILP Approach to Surge Current Minimization in High-Level Synthesis", IEICE Electronics Express, Vol. 6, No. 14, pp. 979-985, 2009. (SCI) (NSC96-2628-E-033-004-MY3)
S.H. Huang, C.M. Chang, and Y.T. Nieh, "Opposite-Phase Register Switching for Peak Current Minimization", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 1, Article 14, 2009. (SCI) (NSC95-2221-E-033-076)
S.H. Huang and C.H. Cheng, "Power-Management Scheduling for Peak Power Minimization", Journal of Information Science and Engineering, Vol. 24, No.6, P.1647-P.1668, 2008. (SCI) (NSC93-2220-E-033-001)
C.H. Cheng, S.H. Huang, and W.P. Tu, "Module Binding for Low Power Clock Gating",IEICE Electronics Express, Vol. 5, No. 18 , pp.762-768, 2008,09. (SCI) (NSC97-2221-E-033-053-MY3)
S.H. Huang and C.H. Cheng, "An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management", IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol.E91-A, No. 1, pp. 375-382, 2008. (SCI) (NSC93-2220-E-033-001)
S.H. Huang*, C.M. Chang, and Y.T. Nieh, "A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains", Journal of Information Science and Engineering, Vol. 23, No. 6, pp.1681-1705, 2007.(SCI) (NSC93-2215-E-033-004)
S.H. Huang and Y.T. Nieh, "Clock Skew Scheduling with Race Conditions Considered", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 12, No. 4, pp.961-976, 2007,09.(SCI) (NSC93-2220-E-033-001)
S.H. Huang and C.H. Cheng, "Operation Scheduling for the Synthesis of False Loop Free Circuits", IEICE Electronics Express, Vol. 4, No. 14, pp.448-454, 2007.(SCI) (NSC93-2220-E-033-001)
S.H. Huang and C.H. Cheng, "An ILP Approach to the Slack Driven Schedulin Problem",IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol.-89-A, No. 6, pp. 1852-1858, 2006. (SCI) (NSC93-2220-E-033-001)
S.H. Huang and Y.T. Nieh, "Synthesis of Nonzero Clock Skew Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 6, pp.961-976, 2006.(SCI) (NSC92-2218-E-033-018)
S.H. Huang and J.Y. Lai, "A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities", IEICE Transactions on Information and Systems, Vol. 88-D, No. 10, pp. 2410-2416, 2005.(SCI) (NSC90-2215-E-033-003)
S.H. Huang and J.Y. Lai, "A High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions", Journal of Information Science and Engineering (JISE), Vol. 21, No. 3, pp. 607-626, 2005.(SCI) (NSC90-2215-E-033-003)
S.H. Huang, C.H. Chiang, and C.H. Cheng, "Three-Dimension Scheduling under Multi-Cycle Interconnect Communications", IEICE Electronics Express, Vol. 2, No. 4, pp. 108-114, 2005. (SCI) (NSC93-2220-E-0333-001)
S.H. Huang, Y.T. Nieh, and C.L. Wang, "An Effective Approach to Designing a Power Distribution Network at the Post-Floorplan Stage", International Journal of Electrical Engineering, Vol. 11, No. 4, pp. 407- 416, 2004.(EI) (NSC90-2215-E-033-003)
S.H. Huang, Y.C. Hsu, and C.C. Lin, "A Timing Driven Crosstalk Optimizer for Gridded Channel Routing", IEICE Transactions on Information and Systems,Vol. 87-D, No. 6 , pp.1575-1581, 2004.(SCI) (NSC89-2218-E-033-023)
S.H. Huang, Y.C. Hsu, and Y.J. Oyang, “A New Scheduling Algorithm for Synthesizing the Control Blocks of Control-Dominated Circuits”, Microprocessing and Microprogramming, Vol. 41, No. 7, pp. 501- 519, 1995. (SCI)
S.H. Huang, C.T. Hwang, Y.C. Hsu, and Y.J. Oyang, “A New Approach to Schedule Operations across Nested-ifs and Nested-loops”, Microprocessing and Microprogramming, Vol. 41, No. 1, pp. 37- 52, 1995. (SCI)

研討會論文

D.Y. Chiu and S.H. Huang, “Dataflow and Hardware Design for The Sharing of Feature Maps”, IEEE International SOC Design Conference (ISOCC), 2022.
C.H. Cheng, S.H. Huang and J.F. Li, “Design and Dataflow for Multibit SRAM-Based MAC Operations”, IEEE International SOC Design Conference (ISOCC), 2022.
H.Y. Kao and S.H. Huang, “A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations”, IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022.
B.X. Lai, S.H. Huang and H.Y. Kao, “A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configurations”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2022.
D.Y. Chiu and S.H. Huang, “Network Pruning by Feature Map Sharing with K-Means Clustering”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2022.
Y.J. Chen and S.H. Huang, “Design Flow for The Implementation of Obfuscated Finite State Machines”, IET International Conference on Engineering Technologies and Applications, 2022.
W.H. Lin, H.Y. Kao and S.H. Huang, “Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators”, IEEE International SOC Design Conference (ISOCC), 2021.
E.H. Zhang and S.H. Huang, “Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing”, IEEE International Conference on Consumer Electronics (ICCE), 2021.
Y.L. Hong, Y.K. Weng and S.H. Huang, “Hardware Implementation for Fending off Side-Channel Attacks”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2021.
Y.K. Weng, S.H. Huang and H.Y. Kao, “Block-Based Compression for Reducing Indexing Cost of DNN Accelerators”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2021.
J.X. Tang, S.H. Huang and J.H. Hung, “ECO Timing Optimization with Data Paths and Clock Paths Considered”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2021
J.H. Hung, S.H. Huang, C.H. Cheng, H.Y. Kao, and W.K. Cheng, “Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers”, IEEE 38th VLSI Test Symposium (VTS), 2020.
W.H. Yang, J.F. Li, C.L. Hsu, C.T. Sun, and S.H. Huang, “A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs”, IEEE 3D Systems Integration Conference (3DIC), 2019.
F.H. Tang, H.Y. Kao, S.H. Huang, and J.F. Li, “3D Test Wrapper Chain Optimization with I/O Cells Binding Considered”, IEEE 3D Systems Integration Conference (3DIC), 2019.
W.H. Lin, H.Y. Kao, and S.H. Huang, “A Design Framework for Hardware Approximation of Deep Neural Networks”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019.
C.H. Chang, E.H. Zhang, and S.H. Huang, “Softsign Function Hardware Implementation Using Piecewise Linear Approximation”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019.
H.Y. Kao, C.H. Hsu, and S.H. Huang, “Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power”, IEEE International Conference on Communication Engineering and Technology (ICCET), 2019.
C.W. Tung, and S.H. Huang, “Low-Power High-Accuracy Approximate Multiplier Using Approximate High-Order Compressors”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019.
C.H. Chang, H.Y. Kao, and S.H. Huang, “Hardware Implementation for Multiple Activation Functions”, IEEE International Conference on Consumer Electronics -Taiwan (ICCE-TW), 2019.
P.C. Chang, and S.H. Huang, “IC Camouflaging by Using Universal Gates under Timing Constraints ”, IEEE International Conference on Consumer Electronics -Taiwan (ICCE-TW), 2019.
W.K. Cheng, J.K. Chen and S.H. Huang, “Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction”, IEEE International Soc Design Conference (ISOCC), 2018.
S.H. Huang, R.B. Lin, M.C. Kim, and S. Nakatake, “Overview of the 2016 CAD Contest at ICCAD”, IEEE International Conference of Computer Aided Design (ICCAD), 2016. (invited paper)
J.R. Chen, A.J. Shih, C.W. Lee, C.H. Cheng, and S.H. Huang, “Layer Assignment for Maximizing The Reliability of 3D ICs”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2016.
W.Z. Cheng, C.H. Cheng, S.H. Huang, “Reliability-Driven High-Level Synthesis with Clock Frequency Considered”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2016.
S.H. Huang, J.Z. Shen, C.H. Cheng, “Layer Assignment for Multi-Power-Mode 3D IC Designs with Power Distribution Networks Considered”, Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), 2016. (MOST 104-2220-E-033-001)
T.J. Wang, S.H. Huang, W.K. Cheng, and Y.C. Chou,"Top-Level Activity-Driven Clock Tree Synthesis with Clock Skew Variation Considered", IEEE International Symposium on Circuits and Systems (ISCAS), 2016. (NSC 102-2221-E-033-064-MY3)
M.H. Hsu, C.H. Cheng, and S.H. Huang, "3D IC Test Scheduling with Test Pads Considered", IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. (MOST 104-2220-E-033-001)
C.H. Chou, Z.Y. Wang, T.Y. Chang, S.H. Huang, and S.C. Chang, "2.5D system synthesis methodology under performance, power and thermal constraints", IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2016.
C.H. Yeh, C.H. Cheng, and S.H. Huang, "Grouping and Placement of Memory BIST Controllers for Test Application Time Minimization", IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. (MOST 104-2220-E-033-001)
C.H. Cheng, S.H. Huang, and T.T. Lin,"Watermark-Strength-Aware Register Binding", IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. (NSC 102-2221-E-033-064-MY3)
N. Viswanathan, S.H. Huang, R.B. Lin, M.C. Kim, “Overview of the 2015 CAD contest at ICCAD”, IEEE International Conference on Computer Aided Design (ICCAD), 2015. (invited paper)
C.C. Chiu and S.H. Huang, “Temperature-Dependent Test Scheduling with TAM Bus Wire Assignment Considered for Core-Based SoC Designs”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2015. (MOST 104-2220-E-033-001)
C.H. Nien, C.H. Cheng, and S.H. Huang, “Test Wrapper Bandwidth Assignment for Minimizing the SoC Test Application Time”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2015. (MOST 104-2220-E-033-001)
T.J. Wang, C.C. Chiu, and S.H. Huang, “Simultaneous Test Scheduling and TAM Bus Wire Assignment for Core-Based SoC Designs “, Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2015.
T.T. Lin, W.P. Tu, and S.H. Huang, "Self-Adjusting Mechanism to Dynamically Suppress the Effect of PVT Variations on Clock Skew", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. (NSC 102-2221-E-033-064-MY3)
H.H. Yeh, C.H. Cheng, and S.H. Huang, "Live Demonstration: A Low-Power High-Level Synthesis System", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. (NSC 97-2221-E-033-053-MY3)
H.H. Yeh, W.P. Tu, J.Z. Shen, T.H. Yeh, and S.H. Huang, "Abstract Bus Interface Unit for ESL Design from TLM 2.0 Communications to the Real Bus Protocol", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014.
H.H. Yeh, C.Y. Huang, S.H. Huang, and Y.T. Nieh, "An Effective and Efficient Approach for Layer Assignment with Thermal Through-Silicon-Vias Planning", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT),2014. (NSC 100-2221-E-033-024-MY3)
H.W. Liao, S.H. Huang, H.H. Yeh, W.P. Tu, “Simultaneous Data Path Synthesis and Clock Skew Scheduling for Leakage and Glitch Power Minimization”, IEEE International Symposium on Next-Generation Electronics (ISNE), 2014. (NSC 99-2221-E-033-061-MY3)
W.P. Tu, S.H. Huang, H.H. Lu, “PVT-Variations-Tolerant Clock Design Using Self-Correcting Adjustable Delay Buffers”, IEEE International Symposium on Next-Generation Electronics (ISNE), 2014. (NSC 102-2221-E-033-064-MY3)
H.H. Yeh, S.H. Huang, Y.T. Nieh, “Leakage-Power-Aware Clock Period Minimization”, IEEE Design Automation & Test in Europe Conference and Exhibition (DATE), 2014. (NSC 99-2221-E-033-061-MY3)
H.H. Yeh, C.Y. Huang, S.H. Huang, "Temperature Rise Minimization through Simultaneous Layer Assignment and Thermal Through-Silicon-Via Planning", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013. (NSC 100-2221-E-033-024-MY3)
S.H. Huang, H.H. Yeh, C.H. Cheng, "Wafer Bonding Type Selection for 3D IC Designs", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013. (NSC 100-2221-E-033-024-MY3)
W.P. Tu, C.H. Chou, S.H. Huang, S.C. Chang, Y.T. Nieh, and C.Y. Chou, "Low-Power Timing Closure Methodology for Ultra-Low Voltage Designs", IEEE International Conference on Computer Aided Design (ICCAD), 2013. (NSC 102-2221-E-033-064-MY3)
W.P. Tu, S.H. Huang, and C.H. Cheng, "Co-Synthesis of Data Paths and Clock Control Paths for Minimum-Period Clock Gating", IEEE Design, Automation & Test in Europe Conference and Exhibition (DATE), 2013. (NSC 99-2221-E-033-061-MY3)
S.H. Huang, W.P. Tu, H.H. Yeh, and M.C. Chi, "An EDA Course Module for the Topic of Reliability Using Automotive Electronics as Applications", Proc. of IEEE Interdisciplinary Engineering Design Education Conference (IEDEC), 2013.
C.H. Cheng, W.S. Tzeng, and S.H. Huang, "Simultaneous WaferBonding Type Selection and Layer Assignment for TSV Count Minimization", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012. (NSC 100-2221-E-033-024-MY3)
H.H. Yeh and S.H. Huang, "Effective and Efficient Layer Assignment for Minimizing The Temperature Rise of Large Three-Dimensional Circuits", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012. (NSC 100-2221-E-033-024-MY3)
H.H. Yeh, S.H. Huang, and C.H. Cheng, "A Formal Approach to Slack-Driven High-Level Synthesis", IEEE International Symposium on Circuits and Systems (ISCAS), 2012. (NSC 99-2221-E-033-061-MY3)
W.P. Tu, S.W. Wu, S.H. Huang, and M.C. Chi, "NBTI-Aware Dual Threshold Voltage Assignment for Leakage Power Reduction", IEEE International Symposium on Circuits and Systems (ISCAS), 2012. (NSC 96-2628-E-033-004-MY3.)
W.P. Tu, S.H. Huang, and C.H. Cheng, "Clock Period Minimization with Minimum Area Overhead in High-Level Synthesis of Nonzero Clock Skew Circuits", IEEE Asia and South Pacific Design Automation Conference (ASP-DAC),P.245-P.250, 2012,01. (NSC99-2221-E-033-061-MY3)
H.H. Yeh, S.H. Huang, and K.H. Li, "3D IC Design Partitioning for Temperature Rise Minimization", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2011. (NSC100-2221-E-033-024-MY3)
W.P. Tu, Y.H. Lee, and S.H. Huang, "TSV Sharing through Multiplexing for TSV Count Minimization in High-Level Synthesis", IEEE International SOC Conference, P.156-P.159, 2011,09. (NSC100-2221-E-033-024-MY3)
S.H. Huang, W.P. Tu, H.H. Yeh, and C.H. Cheng, "Teaching Three-Dimensional System-in-Package Design Automation in a Semester Course", IEEE International Conference on Microelectronic Systems Education, 2011. (NSC100-2221-E-033-024-MY3)
C.H. Cheng, C.H. Kao, and S.H. Huang, "TSV Number Minimization Using Alternative Paths", IEEE International Conference on IC Design & Technology, 2011. (NSC100-2221-E-033-024-MY3)
S.H. Huang, G.Y. Jhuo, and W.L. Huang, "Minimum Buffer Insertions for Clock Period Minimization", IEEE International Symposium on Computer, Communication, Control and Automation, 2010. (NSC97-2221-E-033-053-MY3)
H.H. Yeh, M.C. Chi, and S.H. Huang, "A Design Partitioning Algorithm for Three Dimensional Integrated Circuits", IEEE International Symposium on Computer, Communication, Control and Automation, 2010. (NSC96-2628-E-033-004-MY3)
C.H. Lee, T.Y. Huang, C.H. Cheng, and S.H. Huang, "A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D Ics", IEEE International Symposium on Computer, Communication, Control and Automation, 2010. (NSC97-2221-E-033-053-MY3)
S.H. Huang, C.M. Chang, W.P. Tu, and S.B. Pan, "Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating", IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 2010.(NSC97-2221-E-033-053-MY3)
J.F. Yeh, C.H. Cheng, and S.H. Huang, "Surge Current Minimization in High-Level Synthesis", IEEE International Symposium on Circuits and Systems, 2009. (NSC96-2628-E-033-004-MY3)
S.H. Huang and C.H. Cheng, "Timing Driven Power Gating in High-Level Synthesis", IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2009. (NSC96-2628-E-033-004-MY3)
C.M. Chang, S.H. Huang, Y.K. Ho, J.Z. Lin, and H.P. Wang, Y.S. Lu, "Type-Matching Clock Tree for Zero Skew Clock Gating", IEEE/ACM Design Automation Conference (DAC), 2008.
S.H. Huang, Y.H. Lin, and M.L. Huang, "Utilizing Clock Skew for Timing Reliability Improvement", IEEE TENCON, 2007.
S.H. Huang, C.H. Cheng, C.M. Chang, and Y.T. Nieh, "Clock Period Minimization with Minimum Delay Insertion", IEEE/ACM Desgn Automation Conference (DAC), P.970-P.975, 2007,06. (NSC95-2221-E-033-075-MY2)
S.H. Huang, C.H. Cheng, and C.H. Chiang, "Peak Power Minimization through Power Management Scheduling", IEEE Asia and Pacific Conference on Circuits and Systems, 2006.
S.H. Huang, C.H. Cheng, "Operation Scheduling for False Loop Free Circuits", IEEE Asia and Pacific Conference on Circuits and Systems, 2006.
S.H. Huang, C.M. Chang, and Y.T. Nieh, "State Re-Encoding for Peak Current Minimization", IEEE International Conference on Computer Aided Design (ICCAD), 2006. (NSC95-2221-E-033-076)
S.H. Huang, C.H. Cheng, Y.T. Nieh, and W.C. Yu, "Register Binding for Clock Period Minimization", IEEE Design Automation Conference (DAC) (Best Paper Nomination), 2006. (NSC94-2220-E-033-001)
S.H. Huang, C.M. Chang, and Y.T. Nieh, "Fast Multi-Domain Clock Skew Scheduling for Peak Current Reduction", IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 2006. (NSC93-2215-E-033-004)
S.H. Huang, Y.T. Nieh, and L.P. Lu, "Race-Condition-Aware Clock Skew Scheduling", IEEE Design Automation Conference (DAC), 2005. (NSC93-2220-E-033-001)
Y.T. Nieh, S.H. Huang, and S.Y. Hsu, "Minimizing Peak Current via Opposite-Phase Clock Tree", IEEE Design Automation Conference (DAC), 2005. (NSC93-2220-E-033-001)
S.H. Huang and C.H. Cheng, "A Formal Approach to The Slack Driven Scheduling Problem in High-Level Synthesis", IEEE International Symposium on Circuits and Systems, 2005.
S.H. Huang and Y.R. Chen, "VLSI Implementation of Type-2 Fuzzy Inference Processor", IEEE International Symposium on Circuits and Systems, 2005.
C.H. Lee, C.H. Su, and S.H. Huang, "Floorplanning with Clock Tree Estimation", IEEE International Symposium on Circuits and Systems, 2005. (NSC93-2220-E-033-001)
S.H. Huang, Y.T. Nieh, L.P. Lu, and W.C. Yu, "Race-Condition-Aware Retiming", IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test, 2005.
S.H. Huang and J.Y. Lai, "A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities", IEEE Asia-Pacific Conference on Circuits and Systems, 2004. (Best Paper Candidate)
K.H. Bai and S.H. Huang, "Downlink Base Transmit Station Modulator in WCDMA System", IEEE Asia-Pacific Conference on Circuits and Systems, 2004.
S.H. Huang and Y.T. Nieh,, "Clock Period Minimization of Non-Zero Clock Skew Circuits", IEEE International Conference on Computer Aided Design (ICCAD), pp. 809-812, 2003,11. (NSC91-2215-E-033-005)
S.H. Huang, W.H. Peng, and J.Y. Lai, "Automatic Synthesis of Fuzzy Systems Based on Trapezoid-Shaped Membership Functions", IEEE Asia and Pacific Conference on Circuits and Systems, 2002.
S.H. Huang and Y.C. Hsu, "A Timing Driven Approach for Crosstalk Minimization in Gridded Channel Routing", IEEE Asia and Pacific Conference on Circuits and Systems, 2002.
S.H. Huang and C.L. Wang, "An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints", IEEE International Symposium on Circuits and Systems, 2002.
S.H. Huang and C.L. Wang, "An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints", IEEE International Symposium on Circuits and Systems, 2002.
S.H. Huang, M.C. Chi, and H.M. Hsiao, "An Effective Low Power Design Methodology Based on Interconnect Prediction", IEEE/ACM International Workshop on System-Level Interconnect Prediction, 2001. (NSC89-2218-E-033-023)
M.C. Chi and S.H. Huang, "A Reliable Clock Tree Design Methodology for ASIC Designs", IEEE International Symposium on Quality of Electronic Design, 2000.
M.C. Chi, C. M. Tseng, C.Y. Lee, and S.H. Huang, "A Practical Interconnect Driven ASIC Design Procedure", IEEE International ASIC Conference, 1998.
S.H. Huang, T.Y. Liu, Y.C. Hsu, and Y.J. Oyang, "Synthesis of False Loop Free Circuits", IEEE Asia and South Pacific Design Automation Conference, 1995.
S.H. Huang, Y.L. Jeang, C.T. Hwang, Y.C. Hsu, and J.F. Wang, "A Tree-Based Scheduling Algorithm for Control-Dominated Circuits", IEEE Design Automation Conference, 1993.
S.H. Huang, C.T. Hwang, Y.C. Hsu, and Y.J. Oyang, "A New Approach to Schedule Operations across Nested-ifs and Nested-loops", IEEE/ACM International Symposium on Microarchitecture, 1992.

專利

類別 專利名稱 國別 專利號碼 發明人 專利權人
發明專利 使用相反相位的時鐘樹及其設計方法 中華民國 發明 I287187 號 聶佑庭、許聖裕、黃世旭、張永嘉 中原大學, 工研院
發明專利 暫存器之峰值電流控制方法 中華民國 發明 I323397 號 聶佑庭、黃世旭、張家銘 中原大學, 工研院
發明專利 有限狀態機電路之分解架構 中華民國 發明 I317486 號 曾大誠、林佳宗、張家銘、黃世旭 中原大學
發明專利 在電路中的時脈樹與其合成方法及操作方法 中華民國 發明 I544305 號 聶佑庭、黃世旭、張世杰、周仲韓 中原大學, 工研院, 清華大學
發明專利 Opposite-Phase Scheme for Peak Current Reduction 美國 7352212 聶佑庭、許聖裕、黃世旭、張永嘉 中原大學, 工研院
發明專利 Method for Controlling Peak Current of A Circuit Having A Plurality of Registers 美國 7739625 聶佑庭、黃世旭、張家銘 中原大學, 工研院
發明專利 Methods and Systems for Reducing Clock Skew In a Gated Clock Tree 美國 8086982 張家銘、黃世旭、何元凱、林佳宗、王信博、盧育聖 思源科技
發明專利 Opposite-Phase Scheme for Peak Current Reduction (DIV) 美國 7904874 聶佑庭、許聖裕、黃世旭、張永嘉 中原大學, 工研院
發明專利 Clock Tree in Circuit Having a Power-Mode Control Circuit to Determine a First Delay Time and a Second Delay Time 美國 9477258 聶佑庭、黃世旭、張世杰、周仲韓 中原大學, 工研院, 清華大學
發明專利 乘積累加裝置及其方法 中華民國 發明 I696947 號 黃世旭、董哲瑋 中原大學
發明專利 Multiplication Accumulating Device and Method Thereof 美國 11294632 黃世旭、董哲瑋 中原大學

其他協助產業技術發展之具體績效

  		•  109 年度執行工研院資通所研究計畫「運用特徵圖稀疏性的資料流設計」，進行 AI 加速器資料流設計研究。
  		• 發明專利「乘積累加裝置及其方法」(發明 I696947號) 於2020 台北國際發明暨技術交易展發明競賽獲得金牌獎。
  		• 2018 年 8 月起擔任臺灣積體電路設計學會 (TICD) 理事。
  		• 2018 年 5 月起擔任中華民國消費電子學會 (TCES) 理監事。
  		• 2017年 5 月至 2018 年 10 月擔任科技部 AI 創新研究中心專案計畫推動辦公室共同主持人。
  		• 2015 年擔任「台灣車用電子協會」成立之發起人，並擔任該協會首屆理事。
  		• 發明專利「在電路中的時脈樹與其合成方法及操作方法」(發明 I544305號) 於2017 台北國際發明暨技術交易展發明競賽獲得金牌獎。
  		• 於 104 學年度技術移轉「考慮連線長度之頂層時鐘樹合成」技術予創意電子股份有限公司，並與創意電子股份有限公司執行「考慮製程變異之頂層時鐘樹合成」產學合作研究計畫。
  		• 103 年輔導新竹工業區測試廠商環真科技(經濟部中小企業科技關懷計畫)，提供車用電子可靠度測試規範諮詢與協助技術建立。
  		• 於 102 學年度與工研院資通所 EDA 組進行產學合作，共同研究「可加速電子系統層級 (ESL) 電路開發之匯流排介面單元設計」自動化工具開發，以降低電路設計者在電子系統層級處理匯流排介面所需的設計負擔。
  		• 發明專利「暫存器之峰值電流控制方法」(發明 I323397 號) 入圍 101 年國家發明創作獎決選，並獲得 2012 台北國際發明暨技術交易展發明競賽銀牌獎、2013 年烏克蘭國際發明展金牌獎。
  		• 於 101 學年度與益芯科技(CMSC, Inc.) 執行低功率多電壓時鐘樹合成方法研究之產學合作計畫，此計畫研究成果獲得科技部工程司評選為「應用型產學成果海報展示優良獎」。
  		• 2012 年 8 月至 2013 年 12 月參與工研院資通所設計自動化技術組高階合成(High-Level Synthesis) 之功耗建模與驗證技術開發，提供高階合成微架構探索及最佳化經驗。
  		• 於 95 學年度與思源科技 (Springsoft Inc.) 共同進行閘控制時鐘樹時序差異最小化工具開發之產學合作計畫。此產學合作計畫之成果，主要是提出型態披配時鐘樹設計方法，論文順利發表於 DAC-2008，並已順利獲得美國專利。
  		• 於 ICCAD-2006 提出暫存器重新編碼技術，得以降低峰值電流，目前已獲中華民國發明專利及美國專利，並已實際運用於工研院開發的積體電路。
  		• 於 DAC-2005 提出相反相位時鐘樹，透過平均分配 VDD 及 VSS 的電流，可降低峰值電流，目前已獲中華民國發明專利及美國專利，並已實際運用於工研院開發的積體電路。
  		• 在工研院電通所服務期間，參與執行經濟部科技專案『通訊電子技術發展第二期五年計畫』，進行深次微米積體電路設計自動化流程之研究開發與環境建構，獲得團體研究成果優良獎。
  		• 在工研院電通所服務期間，擔任 FLEX IC 產品開發計畫之計畫主持人，實際參與該 IC 產品之設計、開發、測試及量產，該 IC 產品順利量產，並獲得電通所 BP (Business Program) 重要獎勵。

    專書

    唐經洲、許永和、陳璽煌、林瑞源、黃其泮、黃世旭 ”車用 CAN Bus 網路匯流排系統的理論與實務”（ISBN：978-986-363-016-6），滄海書局（2015年12月）。