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H. Chen, H.-W. Chen, S.-H. Huang, and P.-Y. Chen, “A High-Performance Hardware Design for Polynomial Multiplication in the CRYSTALS-Kyber Algorithm”, Proc. of IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS), pp. 1-6, 2025. |
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Y.-T. Chuan, L.-Y. Su, S.-H. Huang, and J.-F. Li, “Behavioral Model Compiler for Simulating Read Disturbances and Read/Write Errors in STT-MRAMs”, Proc. of IEEE International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 2025. (Best Paper Candidate) |
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Y.-H. Yang, Y.-J. Luo, W.-J. Chen, A.-Y. A. Wu, S.-H. Huang, and M. Berekovic, “PAT-ViT: Token Pruning-based Adversarial Tuning for Robust Vision Transformers”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2025. |
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T.-J. Lin, C.-J. Lin, H.-W. Chen, S.-H. Huang, and P.-Y. Chen, “Efficient Hardware Architecture for SHA3 Hash Function Implementation in CRYSTALS-Kyber”, Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2025. |
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C.-J. Lin and S.-H. Huang, “Clock Skew Scheduling for FSM Protection under Setup-Time Violation-Based Fault Attacks”, Proc. of IEEE International SoC Design Conference (ISOCC), 2025. |
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Y.-S. Lin, C.-J. Lin, Y.-C. Tsai, S.-H. Huang, and P.-Y. Chen, “Runtime-Configurable Off-Stream NTT/INTT Circuit Design for Post-Quantum Cryptography”, Proc. of IEEE International SoC Design Conference (ISOCC), 2025. |
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J.-F. Li, C.-L. Hsu, Y.-G. Chen, T.-Y. Wu, W.-H. Lin, S.-H. Huang, Y.-C. Chia, and Y.-C. Chen, “Effective Design, Modeling and Testing Techniques for Digital Computing-in Memories with MAC Function”, Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2025. |
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Y.-C. Lu and S.-H. Huang, “Analytical Power Consumption Modeling for NOR Flash Memories”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2025. |
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Z.-Y. Huang and S.-H. Huang, “Fault-Tolerant Circuit Design for the Dynamic Operation Unit in RRAM CIM Architecture”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2025. |
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C.-C. Yang, S.-H. Huang, and L.-D. Jeng, “A Machine Learning-Based Approach to Attacking Obfuscated Finite State Machines”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2025. |
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Y.-C. Chen and S.-H. Huang, “Secure Control Logic Design for Dual Key Logic Locking”, Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 800-803, 2024. |
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L.-Y. Su and S.-H. Huang, “Design Flow for Incorporating Camouflaged Logic Gates to Enhance Hardware Security While Considering Timing Closure”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2024. |
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S.-H. Huang, C.-L. Hsiao, and W.-C. Cheng, “Special Session: Enhancing Reliability in Digital Computing-in-Memory Architectures Through Approximation and Fault Tolerance Methods”, Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2024. |
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Y.-C. Lin, L.-Y. Su, and S.-H. Huang, “An Approximate Method for The Fault Tolerance of SRAM-Based Near-Memory Multiply-Accumulate Units”, Proc. of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2024. |
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T.-H. Chen, S.-H. Huang, C.-H. Cheng, and L.-D. Jeng, “Automatic Tool for Translating Sum-of-Product Expressions into Behavior-Level CIM Circuits”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2024. |
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Y.-C. Yu and S.-H. Huang, “Securing Finite State Machines through Obfuscation Modes and Diverse Flip-Flop Configurations”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2024. |
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S.-H. Huang, W.-C. Cheng, and J.-F. Li, “Hardware Trojans of Computing-In-Memories: Issues and Methods”, Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023. |
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M.-S. Wu, Y.-L. Chua, J.-F. Li, Y.-T. Chuan, and S.-H. Huang, “Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs”, Proc. of IEEE International Test Conference in Asia (ITC-Asia), 2023. |
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S.-H. Huang, “A Survey on Hardware Security Techniques for Preventing Reverse Engineering Attacks”, Proc. of IEEE International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 2023. |
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L.-Y. Su and S.-H. Huang, “A Metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2023. |
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H.-C. Lu and S.-H. Huang, “Fault-Tolerant Near-Memory MAC Design with Redundant Memories”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2023. |
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C.-J. Lin, S.-H. Huang, W.-Y. Hsueh, W.-C. Hsu, and C.-W. Su, “An Automatic Facial Analysis System for The Detection of Pediatric Obstructive Sleep Apnea”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2023. |
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Z.-H. Liu, S.-H. Huang, and Y.-T. Chien, “Embedding a Hardware Trojan in The YOLO-v2 Neural Network Model Using FPGA Implementation”, Proc. of IET International Conference on Engineering Technologies and Applications (ICETA), 2023. |
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Y.-C. Chen and S.-H. Huang, “Effective RTL Locking for Obfuscation of Loop-Based Designs”, Proc. of IET International Conference on Engineering Technologies and Applications (ICETA), 2023. |
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H.-Y. Kao and S.-H. Huang, “A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations”, Proc. of IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022. |
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D.-Y. Chiu and S.-H. Huang, “Dataflow and Hardware Design for The Sharing of Feature Maps”, Proc. of IEEE International SOC Design Conference (ISOCC), 2022. |
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C.-H. Cheng, S.-H. Huang and J.-F. Li, “Design and Dataflow for Multibit SRAM-Based MAC Operations”, Proc. of IEEE International SOC Design Conference (ISOCC), 2022. |
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B.-X. Lai, S.-H. Huang and H.-Y. Kao, “A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configurations”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2022. |
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D.-Y. Chiu and S.-H. Huang, “Network Pruning by Feature Map Sharing with K-Means Clustering”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2022. |
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Y.-R. Chen and S.-H. Huang, “Design Flow for The Implementation of Obfuscated Finite State Machines”, Proc. of IET International Conference on Engineering Technologies and Applications (ICETA), 2022. |
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W.-H. Lin, H.-Y. Kao and S.-H. Huang, “Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators”, Proc. of IEEE International SOC Design Conference (ISOCC), 2021. |
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E.-H. Zhang and S.-H. Huang, “Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing”, Proc. of IEEE International Conference on Consumer Electronics (ICCE), 2021. |
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Y.-L. Hong, Y.-K. Weng, and S.-H. Huang, “Hardware Implementation for Fending off Side-Channel Attacks”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2021. |
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Y.-K. Weng, S.-H. Huang, and H.-Y. Kao, “Block-Based Compression for Reducing Indexing Cost of DNN Accelerators”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2021. |
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J.-X. Tang, S.-H. Huang, and J.-H. Hung, “ECO Timing Optimization with Data Paths and Clock Paths Considered”, Proc. of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2021. |
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J.-H. Hung, S.-H. Huang, C.-H. Cheng, H.-Y. Kao, and W.-K. Cheng, “Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers”, Proc. of IEEE VLSI Test Symposium (VTS), 2020. |
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X.-J. Chen and S.-H. Huang, “Low-Power Small-Area 3x3 Convolution Hardware Design”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2020. |
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Y.-H. Wu, W.-H. Lin, and S.-H. Huang, “Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2020. |
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E.-H. Zhang and S.-H. Huang, “A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design”, Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2020. |
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W.-H. Yang, J.-F. Li, C.-L. Hsu, C.-T. Sun, and S.-H. Huang, “A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs”, Proc. of IEEE 3D Systems Integration Conference (3DIC), 2019. |
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F.-H. Tang, H.-Y. Kao, S.-H. Huang, and J.-F. Li, “3D Test Wrapper Chain Optimization with I/O Cells Binding Considered”, IEEE 3D Systems Integration Conference (3DIC), 2019. |
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W.-H. Lin, H.-Y. Kao, and S.-H. Huang, “A Design Framework for Hardware Approximation of Deep Neural Networks”, Proc. of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019. |
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C.-H. Chang, E.-H. Zhang, and S.-H. Huang, “Softsign Function Hardware Implementation Using Piecewise Linear Approximation”, Proc. of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019. |
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H.-Y. Kao, C.-H. Hsu, and S.-H. Huang, “Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power”, Proc. of IEEE International Conference on Communication Engineering and Technology (ICCET), 2019. |
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C.-W. Tung, and S.-H. Huang, “Low-Power High-Accuracy Approximate Multiplier Using Approximate High-Order Compressors”, Proc. of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019. |
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C.-H. Chang, H.-Y. Kao, and S.-H. Huang, “Hardware Implementation for Multiple Activation Functions”, Proc. of IEEE International Conference on Consumer Electronics -Taiwan (ICCE-TW), 2019. |
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P.-C. Chang, and S.-H. Huang, “IC Camouflaging by Using Universal Gates under Timing Constraints”, Proc. of IEEE International Conference on Consumer Electronics -Taiwan (ICCE-TW), 2019. |
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S.-H. Huang, “Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization”, Proc. of IEEE International Workshop on Network on Chip Architectures (NoCArc), 2018. |
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Y.-Y. Wu and S.-H. Huang, “TSV-Aware 3D Test Wrapper Chain Optimization”, Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2018. (Best Paper Candidate) |
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C.-H. Lin, S.-H. Huang, and W.-K. Cheng, “An Effective Approach for Building Low-Power General Activity-Driven Clock Trees”, Proc. of IEEE International Soc Design Conference (ISOCC), 2018. |
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W.-K. Cheng, J.-K. Chen and S.-H. Huang, “Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction”, Proc. of IEEE International Soc Design Conference (ISOCC), 2018. |
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M.-C. Kim, S.-H. Huang, R.-B. Lin, and S. Nakatake, “Overview of the 2017 CAD contest at ICCAD”, Proc. of IEEE International Conference on Computer-Aided Design (ICCAD), 2017. |
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Y.-C. Ko and S.-H. Huang, “3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints”, Proc. of IEEE Asian Test Symposium (ATS), 2017. |
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S.-H. Huang, R.-B. Lin, M.-C. Kim, and S. Nakatake, “Overview of the 2016 CAD Contest at ICCAD”, Proc. of IEEE International Conference on Computer-Aided Design (ICCAD), 2016. |
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T.-J. Wang, S.-H. Huang, W.-K. Cheng, and Y.-C. Chou, “Top-Level Activity-Driven Clock Tree Synthesis with Clock Skew Variation Considered”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2016. |
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J.-R. Chen, A.-J. Shih, C.-W. Lee, C.-H. Cheng, and S.-H. Huang, “Layer Assignment for Maximizing The Reliability of 3D ICs”, Proc. of IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2016. |
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W.-Z. Cheng, C.-H. Cheng, S.-H. Huang, “Reliability-Driven High-Level Synthesis with Clock Frequency Considered”, Proc. of IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2016. |
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M.-H. Hsu, C.-H. Cheng, and S.-H. Huang, “3D IC Test Scheduling with Test Pads Considered”, IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. |
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C.-H. Yeh, C.-H. Cheng, and S.-H. Huang, “Grouping and Placement of Memory BIST Controllers for Test Application Time Minimization”, Proc. of IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. |
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C.-H. Cheng, S.-H. Huang, and T.-T. Lin, “Watermark-Strength-Aware Register Binding”, Proc. of IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. |
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C.-H. Chou, Z.-Y. Wang, T.-Y. Chang, S.-H. Huang, and S.-C. Chang, "2.5D System Synthesis Methodology under Performance, Power and Thermal Constraints", Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2016. |
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N. Viswanathan, S.-H. Huang, R.-B. Lin, and M.-C. Kim, “Overview of the 2015 CAD contest at ICCAD”, Proc. of IEEE International Conference on Computer-Aided Design (ICCAD), 2015. |
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C.-C. Chiu and S.-H. Huang, “Temperature-Dependent Test Scheduling with TAM Bus Wire Assignment Considered for Core-Based SoC Designs”, Proc. of IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2015. |
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C.-H. Nien, C.-H. Cheng, and S.-H. Huang, “Test Wrapper Bandwidth Assignment for Minimizing the SoC Test Application Time”, Proc. of IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2015. |
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H.-H. Yeh, S.-H. Huang, and Y.-T. Nieh, “Leakage-Power-Aware Clock Period Minimization”, Proc. of IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. |
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T.-T. Lin, W.-P. Tu, and S.-H. Huang, “Self-Adjusting Mechanism to Dynamically Suppress the Effect of PVT Variations on Clock Skew”, Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. |
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H.-H. Yeh, W.-P. Tu, J.-Z. Shen, T.-H. Yeh, and S.-H. Huang, “Abstract Bus Interface Unit for ESL Design from TLM 2.0 Communications to the Real Bus Protocol”, Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. |
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H.-H. Yeh, C.-H. Cheng, and S.-H. Huang, “Live Demonstration: A Low-Power High-Level Synthesis System”, Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. |
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H.-H. Yeh, C.-Y. Huang, S.-H. Huang, and Y.-T. Nieh, “An Effective and Efficient Approach for Layer Assignment with Thermal Through-Silicon-Vias Planning”, IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT),2014. |
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H.-W. Liao, S.-H. Huang, H.-H. Yeh, W.-P. Tu, “Simultaneous Data Path Synthesis and Clock Skew Scheduling for Leakage and Glitch Power Minimization”, Proc. of IEEE International Symposium on Next-Generation Electronics (ISNE), 2014. |
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W.-P. Tu, S.-H. Huang, and H.-H. Lu, “PVT-Variations-Tolerant Clock Design Using Self-Correcting Adjustable Delay Buffers”, Proc. of IEEE International Symposium on Next-Generation Electronics (ISNE), 2014. |
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W.-P. Tu, C.-H. Chou, S.-H. Huang, S.-C. Chang, Y.-T. Nieh, and C.-Y. Chou, “Low-Power Timing Closure Methodology for Ultra-Low Voltage Designs”, Proc. of IEEE International Conference on Computer Aided Design (ICCAD), 2013. |
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W.-P. Tu, S.-H. Huang and C.-H. Cheng, “Co-Synthesis of Data Paths and Clock Control Paths for Minimum-Period Clock Gating”, Proc. of IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1831-1836, 2013. |
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H.-H. Yeh, C.-Y. Huang, and S.-H. Huang, “Temperature Rise Minimization through Simultaneous Layer Assignment and Thermal Through-Silicon-Via Planning”, Proc. of IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013. |
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S.-H. Huang, H.-H. Yeh, and C.-H. Cheng, “Wafer Bonding Type Selection for 3D IC Designs”, Proc. of IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013. |
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S.-H. Huang, W.-P. Tu, H.-H. Yeh, and M.C. Chi, “An EDA Course Module for the Topic of Reliability Using Automotive Electronics as Applications”, Proc. of IEEE Interdisciplinary Engineering Design Education Conference (IEDEC), 2013. |
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W.-P. Tu, S.-H. Huang, and C.-H. Cheng, “Clock Period Minimization with Minimum Area Overhead in High-Level Synthesis of Nonzero Clock Skew Circuits”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 245-250, 2012. |
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H.-H. Yeh, S.-H. Huang, and C.H. Cheng, “A Formal Approach to Slack-Driven High-Level Synthesis”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2012. |
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W.-P. Tu, S.-W. Wu, S.-H. Huang, and M.C. Chi, “NBTI-Aware Dual Threshold Voltage Assignment for Leakage Power Reduction”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2012. |
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C.-H. Cheng, W.-S. Tzeng, and S.-H. Huang, “Simultaneous Wafer Bonding Type Selection and Layer Assignment for TSV Count Minimization”, Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012. |
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H.-H. Yeh and S.-H. Huang, “Effective and Efficient Layer Assignment for Minimizing The Temperature Rise of Large Three-Dimensional Circuits”, Proc. of IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012. |
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H.-H. Yeh, S.-H. Huang, and K.-H. Li, “3D IC Design Partitioning for Temperature Rise Minimization”, Proc. of IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011. |
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W.-P. Tu, Y.-H. Lee, and S.-H. Huang, “TSV Sharing through Multiplexing for TSV Count Minimization in High-Level Synthesis”, Proc. of IEEE International SOC Conference (SOCC), pp. 156-159, 2011. |
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C.-H. Cheng, C.-H. Kao, and S.-H. Huang, “TSV Number Minimization Using Alternative Paths”, Proc. of IEEE International Conference on IC Design & Technology (ICICDT), 2011. |
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S.-H. Huang, W.-P. Tu, H.-H. Yeh, and C.-H. Cheng, “Teaching Three-Dimensional System-in-Package Design Automation in a Semester Course”, Proc. of IEEE International Conference on Microelectronic Systems Education (MSE), 2011. |
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S.-H. Huang, C.-M. Chang, W.-P. Tu and S.-B. Pan, “Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 480-485, 2010. |
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S.-H. Huang, G.-Y. Jhuo, and W.-L. Huang, “Minimum Buffer Insertions for Clock Period Minimization”, Proc. of IEEE International Symposium on Computer, Communication, Control and Automation, 2010. |
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H.-H. Yeh, M.C. Chi, and S.-H. Huang, “A Design Partitioning Algorithm for Three Dimensional Integrated Circuits”, Proc. of IEEE International Symposium on Computer, Communication, Control and Automation, 2010. |
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C.-H. Lee, T.-Y. Huang, C.-H. Cheng, and S.-H. Huang, “A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D ICs”, Proc. of IEEE International Symposium on Computer, Communication, Control and Automation, 2010. |
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S.-H. Huang and C.-H. Cheng, “Timing Driven Power Gating in High-Level Synthesis”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2009. |
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J.-F. Yeh, C.-H. Cheng, and S.-H. Huang, "Surge Current Minimization in High-Level Synthesis", IEEE International Symposium on Circuits and Systems (ISCAS), 2009. |
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C.-M. Chang, S.-H. Huang, Y.-K. Ho, J.-Z. Lin, and H.-P. Wang, Y.-S. Lu, “Type-Matching Clock Tree for Zero Skew Clock Gating”, Proc. of IEEE Design Automation Conference (DAC), pp. 714-719, 2008. |
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S.-H. Huang, C.-H. Cheng, C.-H. Chang, and Y.-T. Nieh, “Clock Period Minimization with Minimum Delay Insertion”, Proc. of IEEE Design Automation Conference (DAC),2007. |
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S.-H. Huang, Y.-H. Lin, and M.-L. Huang, “Utilizing Clock Skew for Timing Reliability Improvement”, Proc. of IEEE Region 10 Conference (TENCON), 2007. |
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S.-H. Huang, C.-M. Chang, and Y.-T. Nieh, “State Re-Encoding for Peak Current Minimization”, Proc. of IEEE International Conference on Computer-Aided Design (ICCAD), 2006. |
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S.-H. Huang, C.-H. Cheng, Y.-T. Nieh and W.-C. Yu, “Register Binding for Clock Period Minimization”, Proc. of IEEE Design Automation Conference (DAC), pp. 439-444, 2006. (Best Paper Candidate) |
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S.-H. Huang, C.-M. Chang, and Y.-T. Nieh, “Fast Multi-Domain Clock Skew Scheduling for Peak Current Reduction”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2006. |
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S.-H. Huang, C.-H. Cheng, and C.-H. Chiang, “Peak Power Minimization through Power Management Scheduling”, Proc. of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS), 2006. |
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S.-H. Huang, C.H. Cheng, “Operation Scheduling for False Loop Free Circuits”, Proc. of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS), 2006. |
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S.-H. Huang, Y.-T. Nieh, and F.-P. Lu, “Race-Condition-Aware Clock Skew Scheduling”, Proc. of IEEE Design Automation Conference (DAC), 2005. |
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Y.-T. Nieh, S.-H. Huang, and S.-Y. Hsu, “Minimizing Peak Current via Opposite-Phase Clock Tree”, Proc. of IEEE Design Automation Conference (DAC), 2005. |
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S.-H. Huang and C.-H. Cheng, “A Formal Approach to The Slack Driven Scheduling Problem in High-Level Synthesis”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2005. |
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S.-H. Huang and Y.-R. Chen, “VLSI Implementation of Type-2 Fuzzy Inference Processor”, Proc. of IEEE International Symposium on Circuits and Systems, 2005. |
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C.-H. Lee, C.-H. Su, and S.-H. Huang, “Floorplanning with Clock Tree Estimation”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2005. |
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S.-H. Huang, Y.-T. Nieh, L.-P. Lu, and W.-C. Yu, “Race-Condition-Aware Retiming”, Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2005. |
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S.-H. Huang and J.-Y. Lai, “A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities”, Proc. of IEEE Asia-Pacific Conference on Circuits and Systems, 2004. (Best Paper Candidate) |
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K.-H. Bai and S.-H. Huang, “Downlink Base Transmit Station Modulator in WCDMA System”, Proc. of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 2004. |
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S.-H. Huang and Y.-T. Nieh, “Clock Period Minimization of Non-Zero Clock Skew Circuits”, Proc. of IEEE International Conference on Computer Aided Design (ICCAD), 2003. |
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S.-H. Huang and C.-L. Wang, “An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2002. |
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S.-H. Huang, W.-H. Peng, and J.-Y. Lai, “Automatic Synthesis of Fuzzy Systems Based on Trapezoid-Shaped Membership Functions”, Proc. of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS), 2002. |
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S.-H. Huang and Y.-C. Hsu, “A Timing Driven Approach for Crosstalk Minimization in Gridded Channel Routing”, Proc. of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS), 2002. |
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S.-H. Huang, M.C. Chi, and H.-M. Hsiao, “An Effective Low Power Design Methodology Based on Interconnect Prediction”, Proc. of IEEE International Workshop on System-Level Interconnect Prediction (SLIP), 2001. |
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M.C. Chi and S.-H. Huang, “A Reliable Clock Tree Design Methodology for ASIC Designs”, Proc. of IEEE International Symposium on Quality of Electronic Design (ISQED), 2000. |
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M.C. Chi, C.-M. Tseng, C.-Y. Lee, and S.-H. Huang, “A Practical Interconnect Driven ASIC Design Procedure”, Proc. of IEEE International ASIC Conference, 1998. |
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S.-H. Huang, T.-Y. Liu, Y.-C. Hsu, and Y.-J. Oyang, “Synthesis of False Loop Free Circuits”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 1995. |
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S.-H. Huang, Y.-L. Jeang, C.-T. Hwang, Y.-C. Hsu, and J.-F. Wang, “A Tree-Based Scheduling Algorithm for Control-Dominated Circuits”, Proc. of IEEE Design Automation Conference (DAC), 1993. |
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S.-H. Huang, C.-T. Hwang, Y.-C. Hsu, and Y.-J. Oyang, “A New Approach to Schedule Operations across Nested-ifs and Nested-loops”, Proc. of IEEE International Symposium on Microarchitecture (MICRO), 1992. |
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D.Y. Chiu and S.H. Huang, “Dataflow and Hardware Design for The Sharing of Feature Maps”, IEEE International SOC Design Conference (ISOCC), 2022. |
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C.H. Cheng, S.H. Huang and J.F. Li, “Design and Dataflow for Multibit SRAM-Based MAC Operations”, IEEE International SOC Design Conference (ISOCC), 2022. |
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H.Y. Kao and S.H. Huang, “A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations”, IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022. |
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B.X. Lai, S.H. Huang and H.Y. Kao, “A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configurations”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2022. |
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D.Y. Chiu and S.H. Huang, “Network Pruning by Feature Map Sharing with K-Means Clustering”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2022. |
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Y.J. Chen and S.H. Huang, “Design Flow for The Implementation of Obfuscated Finite State Machines”, IET International Conference on Engineering Technologies and Applications, 2022. |
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W.H. Lin, H.Y. Kao and S.H. Huang, “Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators”, IEEE International SOC Design Conference (ISOCC), 2021. |
|
E.H. Zhang and S.H. Huang, “Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing”, IEEE International Conference on Consumer Electronics (ICCE), 2021. |
|
Y.L. Hong, Y.K. Weng and S.H. Huang, “Hardware Implementation for Fending off Side-Channel Attacks”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2021. |
|
Y.K. Weng, S.H. Huang and H.Y. Kao, “Block-Based Compression for Reducing Indexing Cost of DNN Accelerators”, IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2021. |
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J.X. Tang, S.H. Huang and J.H. Hung, “ECO Timing Optimization with Data Paths and Clock Paths Considered”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2021 |
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J.H. Hung, S.H. Huang, C.H. Cheng, H.Y. Kao, and W.K. Cheng, “Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers”, IEEE 38th VLSI Test Symposium (VTS), 2020. |
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W.H. Yang, J.F. Li, C.L. Hsu, C.T. Sun, and S.H. Huang, “A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs”, IEEE 3D Systems Integration Conference (3DIC), 2019. |
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F.H. Tang, H.Y. Kao, S.H. Huang, and J.F. Li, “3D Test Wrapper Chain Optimization with I/O Cells Binding Considered”, IEEE 3D Systems Integration Conference (3DIC), 2019. |
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W.H. Lin, H.Y. Kao, and S.H. Huang, “A Design Framework for Hardware Approximation of Deep Neural Networks”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019. |
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C.H. Chang, E.H. Zhang, and S.H. Huang, “Softsign Function Hardware Implementation Using Piecewise Linear Approximation”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019. |
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H.Y. Kao, C.H. Hsu, and S.H. Huang, “Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power”, IEEE International Conference on Communication Engineering and Technology (ICCET), 2019. |
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C.W. Tung, and S.H. Huang, “Low-Power High-Accuracy Approximate Multiplier Using Approximate High-Order Compressors”, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2019. |
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C.H. Chang, H.Y. Kao, and S.H. Huang, “Hardware Implementation for Multiple Activation Functions”, IEEE International Conference on Consumer Electronics -Taiwan (ICCE-TW), 2019. |
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P.C. Chang, and S.H. Huang, “IC Camouflaging by Using Universal Gates under Timing Constraints ”, IEEE International Conference on Consumer Electronics -Taiwan (ICCE-TW), 2019. |
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W.K. Cheng, J.K. Chen and S.H. Huang, “Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction”, IEEE International Soc Design Conference (ISOCC), 2018. |
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S.H. Huang, R.B. Lin, M.C. Kim, and S. Nakatake, “Overview of the 2016 CAD Contest at ICCAD”, IEEE International Conference of Computer Aided Design (ICCAD), 2016. (invited paper) |
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J.R. Chen, A.J. Shih, C.W. Lee, C.H. Cheng, and S.H. Huang, “Layer Assignment for Maximizing The Reliability of 3D ICs”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2016. |
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W.Z. Cheng, C.H. Cheng, S.H. Huang, “Reliability-Driven High-Level Synthesis with Clock Frequency Considered”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2016. |
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S.H. Huang, J.Z. Shen, C.H. Cheng, “Layer Assignment for Multi-Power-Mode 3D IC Designs with Power Distribution Networks Considered”, Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), 2016. (MOST 104-2220-E-033-001) |
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T.J. Wang, S.H. Huang, W.K. Cheng, and Y.C. Chou,"Top-Level Activity-Driven Clock Tree Synthesis with Clock Skew Variation Considered", IEEE International Symposium on Circuits and Systems (ISCAS), 2016. (NSC 102-2221-E-033-064-MY3) |
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M.H. Hsu, C.H. Cheng, and S.H. Huang, "3D IC Test Scheduling with Test Pads Considered", IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. (MOST 104-2220-E-033-001) |
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C.H. Chou, Z.Y. Wang, T.Y. Chang, S.H. Huang, and S.C. Chang, "2.5D system synthesis methodology under performance, power and thermal constraints", IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2016. |
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C.H. Yeh, C.H. Cheng, and S.H. Huang, "Grouping and Placement of Memory BIST Controllers for Test Application Time Minimization", IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. (MOST 104-2220-E-033-001) |
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C.H. Cheng, S.H. Huang, and T.T. Lin,"Watermark-Strength-Aware Register Binding", IEEE International Symposium on Next-Generation Electronics (ISNE), 2016. (NSC 102-2221-E-033-064-MY3) |
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N. Viswanathan, S.H. Huang, R.B. Lin, M.C. Kim, “Overview of the 2015 CAD contest at ICCAD”, IEEE International Conference on Computer Aided Design (ICCAD), 2015. (invited paper) |
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C.C. Chiu and S.H. Huang, “Temperature-Dependent Test Scheduling with TAM Bus Wire Assignment Considered for Core-Based SoC Designs”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2015. (MOST 104-2220-E-033-001) |
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C.H. Nien, C.H. Cheng, and S.H. Huang, “Test Wrapper Bandwidth Assignment for Minimizing the SoC Test Application Time”, IEEE International Symposium on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), 2015. (MOST 104-2220-E-033-001) |
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T.J. Wang, C.C. Chiu, and S.H. Huang, “Simultaneous Test Scheduling and TAM Bus Wire Assignment for Core-Based SoC Designs “, Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2015. |
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T.T. Lin, W.P. Tu, and S.H. Huang, "Self-Adjusting Mechanism to Dynamically Suppress the Effect of PVT Variations on Clock Skew", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. (NSC 102-2221-E-033-064-MY3) |
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H.H. Yeh, C.H. Cheng, and S.H. Huang, "Live Demonstration: A Low-Power High-Level Synthesis System", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. (NSC 97-2221-E-033-053-MY3) |
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H.H. Yeh, W.P. Tu, J.Z. Shen, T.H. Yeh, and S.H. Huang, "Abstract Bus Interface Unit for ESL Design from TLM 2.0 Communications to the Real Bus Protocol", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014. |
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H.H. Yeh, C.Y. Huang, S.H. Huang, and Y.T. Nieh, "An Effective and Efficient Approach for Layer Assignment with Thermal Through-Silicon-Vias Planning", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT),2014. (NSC 100-2221-E-033-024-MY3) |
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H.W. Liao, S.H. Huang, H.H. Yeh, W.P. Tu, “Simultaneous Data Path Synthesis and Clock Skew Scheduling for Leakage and Glitch Power Minimization”, IEEE International Symposium on Next-Generation Electronics (ISNE), 2014. (NSC 99-2221-E-033-061-MY3) |
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W.P. Tu, S.H. Huang, H.H. Lu, “PVT-Variations-Tolerant Clock Design Using Self-Correcting Adjustable Delay Buffers”, IEEE International Symposium on Next-Generation Electronics (ISNE), 2014. (NSC 102-2221-E-033-064-MY3) |
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H.H. Yeh, S.H. Huang, Y.T. Nieh, “Leakage-Power-Aware Clock Period Minimization”, IEEE Design Automation & Test in Europe Conference and Exhibition (DATE), 2014. (NSC 99-2221-E-033-061-MY3) |
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H.H. Yeh, C.Y. Huang, S.H. Huang, "Temperature Rise Minimization through Simultaneous Layer Assignment and Thermal Through-Silicon-Via Planning", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013. (NSC 100-2221-E-033-024-MY3) |
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S.H. Huang, H.H. Yeh, C.H. Cheng, "Wafer Bonding Type Selection for 3D IC Designs", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013. (NSC 100-2221-E-033-024-MY3) |
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W.P. Tu, C.H. Chou, S.H. Huang, S.C. Chang, Y.T. Nieh, and C.Y. Chou, "Low-Power Timing Closure Methodology for Ultra-Low Voltage Designs", IEEE International Conference on Computer Aided Design (ICCAD), 2013. (NSC 102-2221-E-033-064-MY3) |
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W.P. Tu, S.H. Huang, and C.H. Cheng, "Co-Synthesis of Data Paths and Clock Control Paths for Minimum-Period Clock Gating", IEEE Design, Automation & Test in Europe Conference and Exhibition (DATE), 2013. (NSC 99-2221-E-033-061-MY3) |
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S.H. Huang, W.P. Tu, H.H. Yeh, and M.C. Chi, "An EDA Course Module for the Topic of Reliability Using Automotive Electronics as Applications", Proc. of IEEE Interdisciplinary Engineering Design Education Conference (IEDEC), 2013. |
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C.H. Cheng, W.S. Tzeng, and S.H. Huang, "Simultaneous WaferBonding Type Selection and Layer Assignment for TSV Count Minimization", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012. (NSC 100-2221-E-033-024-MY3) |
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H.H. Yeh and S.H. Huang, "Effective and Efficient Layer Assignment for Minimizing The Temperature Rise of Large Three-Dimensional Circuits", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012. (NSC 100-2221-E-033-024-MY3) |
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H.H. Yeh, S.H. Huang, and C.H. Cheng, "A Formal Approach to Slack-Driven High-Level Synthesis", IEEE International Symposium on Circuits and Systems (ISCAS), 2012. (NSC 99-2221-E-033-061-MY3) |
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W.P. Tu, S.W. Wu, S.H. Huang, and M.C. Chi, "NBTI-Aware Dual Threshold Voltage Assignment for Leakage Power Reduction", IEEE International Symposium on Circuits and Systems (ISCAS), 2012. (NSC 96-2628-E-033-004-MY3.) |
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W.P. Tu, S.H. Huang, and C.H. Cheng, "Clock Period Minimization with Minimum Area Overhead in High-Level Synthesis of Nonzero Clock Skew Circuits", IEEE Asia and South Pacific Design Automation Conference (ASP-DAC),P.245-P.250, 2012,01. (NSC99-2221-E-033-061-MY3) |
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H.H. Yeh, S.H. Huang, and K.H. Li, "3D IC Design Partitioning for Temperature Rise Minimization", IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2011. (NSC100-2221-E-033-024-MY3) |
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W.P. Tu, Y.H. Lee, and S.H. Huang, "TSV Sharing through Multiplexing for TSV Count Minimization in High-Level Synthesis", IEEE International SOC Conference, P.156-P.159, 2011,09. (NSC100-2221-E-033-024-MY3) |
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S.H. Huang, W.P. Tu, H.H. Yeh, and C.H. Cheng, "Teaching Three-Dimensional System-in-Package Design Automation in a Semester Course", IEEE International Conference on Microelectronic Systems Education, 2011. (NSC100-2221-E-033-024-MY3) |
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C.H. Cheng, C.H. Kao, and S.H. Huang, "TSV Number Minimization Using Alternative Paths", IEEE International Conference on IC Design & Technology, 2011. (NSC100-2221-E-033-024-MY3) |
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S.H. Huang, G.Y. Jhuo, and W.L. Huang, "Minimum Buffer Insertions for Clock Period Minimization", IEEE International Symposium on Computer, Communication, Control and Automation, 2010. (NSC97-2221-E-033-053-MY3) |
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H.H. Yeh, M.C. Chi, and S.H. Huang, "A Design Partitioning Algorithm for Three Dimensional Integrated Circuits", IEEE International Symposium on Computer, Communication, Control and Automation, 2010. (NSC96-2628-E-033-004-MY3) |
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C.H. Lee, T.Y. Huang, C.H. Cheng, and S.H. Huang, "A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D Ics", IEEE International Symposium on Computer, Communication, Control and Automation, 2010. (NSC97-2221-E-033-053-MY3) |
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S.H. Huang, C.M. Chang, W.P. Tu, and S.B. Pan, "Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating", IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 2010.(NSC97-2221-E-033-053-MY3) |
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J.F. Yeh, C.H. Cheng, and S.H. Huang, "Surge Current Minimization in High-Level Synthesis", IEEE International Symposium on Circuits and Systems, 2009. (NSC96-2628-E-033-004-MY3) |
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S.H. Huang and C.H. Cheng, "Timing Driven Power Gating in High-Level Synthesis", IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2009. (NSC96-2628-E-033-004-MY3) |
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C.M. Chang, S.H. Huang, Y.K. Ho, J.Z. Lin, and H.P. Wang, Y.S. Lu, "Type-Matching Clock Tree for Zero Skew Clock Gating", IEEE/ACM Design Automation Conference (DAC), 2008. |
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S.H. Huang, Y.H. Lin, and M.L. Huang, "Utilizing Clock Skew for Timing Reliability Improvement", IEEE TENCON, 2007. |
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S.H. Huang, C.H. Cheng, C.M. Chang, and Y.T. Nieh, "Clock Period Minimization with Minimum Delay Insertion", IEEE/ACM Desgn Automation Conference (DAC), P.970-P.975, 2007,06. (NSC95-2221-E-033-075-MY2) |
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S.H. Huang, C.H. Cheng, and C.H. Chiang, "Peak Power Minimization through Power Management Scheduling", IEEE Asia and Pacific Conference on Circuits and Systems, 2006. |
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S.H. Huang, C.H. Cheng, "Operation Scheduling for False Loop Free Circuits", IEEE Asia and Pacific Conference on Circuits and Systems, 2006. |
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S.H. Huang, C.M. Chang, and Y.T. Nieh, "State Re-Encoding for Peak Current Minimization", IEEE International Conference on Computer Aided Design (ICCAD), 2006. (NSC95-2221-E-033-076) |
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S.H. Huang, C.H. Cheng, Y.T. Nieh, and W.C. Yu, "Register Binding for Clock Period Minimization", IEEE Design Automation Conference (DAC) (Best Paper Nomination), 2006. (NSC94-2220-E-033-001) |
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S.H. Huang, C.M. Chang, and Y.T. Nieh, "Fast Multi-Domain Clock Skew Scheduling for Peak Current Reduction", IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 2006. (NSC93-2215-E-033-004) |
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S.H. Huang, Y.T. Nieh, and L.P. Lu, "Race-Condition-Aware Clock Skew Scheduling", IEEE Design Automation Conference (DAC), 2005. (NSC93-2220-E-033-001) |
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Y.T. Nieh, S.H. Huang, and S.Y. Hsu, "Minimizing Peak Current via Opposite-Phase Clock Tree", IEEE Design Automation Conference (DAC), 2005. (NSC93-2220-E-033-001) |
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S.H. Huang and C.H. Cheng, "A Formal Approach to The Slack Driven Scheduling Problem in High-Level Synthesis", IEEE International Symposium on Circuits and Systems, 2005. |
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S.H. Huang and Y.R. Chen, "VLSI Implementation of Type-2 Fuzzy Inference Processor", IEEE International Symposium on Circuits and Systems, 2005. |
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C.H. Lee, C.H. Su, and S.H. Huang, "Floorplanning with Clock Tree Estimation", IEEE International Symposium on Circuits and Systems, 2005. (NSC93-2220-E-033-001) |
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S.H. Huang, Y.T. Nieh, L.P. Lu, and W.C. Yu, "Race-Condition-Aware Retiming", IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test, 2005. |
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S.H. Huang and J.Y. Lai, "A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities", IEEE Asia-Pacific Conference on Circuits and Systems, 2004. (Best Paper Candidate) |
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K.H. Bai and S.H. Huang, "Downlink Base Transmit Station Modulator in WCDMA System", IEEE Asia-Pacific Conference on Circuits and Systems, 2004. |
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S.H. Huang and Y.T. Nieh,, "Clock Period Minimization of Non-Zero Clock Skew Circuits", IEEE International Conference on Computer Aided Design (ICCAD), pp. 809-812, 2003,11. (NSC91-2215-E-033-005) |
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S.H. Huang, W.H. Peng, and J.Y. Lai, "Automatic Synthesis of Fuzzy Systems Based on Trapezoid-Shaped Membership Functions", IEEE Asia and Pacific Conference on Circuits and Systems, 2002. |
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S.H. Huang and Y.C. Hsu, "A Timing Driven Approach for Crosstalk Minimization in Gridded Channel Routing", IEEE Asia and Pacific Conference on Circuits and Systems, 2002. |
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S.H. Huang and C.L. Wang, "An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints", IEEE International Symposium on Circuits and Systems, 2002. |
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S.H. Huang and C.L. Wang, "An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints", IEEE International Symposium on Circuits and Systems, 2002. |
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S.H. Huang, M.C. Chi, and H.M. Hsiao, "An Effective Low Power Design Methodology Based on Interconnect Prediction", IEEE/ACM International Workshop on System-Level Interconnect Prediction, 2001. (NSC89-2218-E-033-023) |
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M.C. Chi and S.H. Huang, "A Reliable Clock Tree Design Methodology for ASIC Designs", IEEE International Symposium on Quality of Electronic Design, 2000. |
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M.C. Chi, C. M. Tseng, C.Y. Lee, and S.H. Huang, "A Practical Interconnect Driven ASIC Design Procedure", IEEE International ASIC Conference, 1998. |
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S.H. Huang, T.Y. Liu, Y.C. Hsu, and Y.J. Oyang, "Synthesis of False Loop Free Circuits", IEEE Asia and South Pacific Design Automation Conference, 1995. |
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S.H. Huang, Y.L. Jeang, C.T. Hwang, Y.C. Hsu, and J.F. Wang, "A Tree-Based Scheduling Algorithm for Control-Dominated Circuits", IEEE Design Automation Conference, 1993. |
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S.H. Huang, C.T. Hwang, Y.C. Hsu, and Y.J. Oyang, "A New Approach to Schedule Operations across Nested-ifs and Nested-loops", IEEE/ACM International Symposium on Microarchitecture, 1992. |